Insulated gate field effect transistors (IGFETs) typically include a channel region in which current is controlled through the application of an electrical bias to a gate electrode that is separated from the channel region by a thin insulating film or gate dielectric. Current through the channel is supplied and collected by source and drain contacts, respectively. As semiconductor devices become increasingly miniaturized, gate dielectrics having a reduced equivalent oxide thickness (EOT) may be desirable. For example, the Semiconductor Industry Association (SIA) National Technology Roadmap for Semiconductors (NTRS) has projected that gate dielectrics with an EOT below 1 nm may be desirable for uses such as in advanced complementary metal-semiconductor oxide field effect transistor (CMOS FET) devices having channel lengths scaled to below 50 nm. However, reduced EOT dielectrics may exhibit relatively high levels of tunneling leakage current. For example, tunneling of conventional materials such as SiO2 may exceed 1-5 A/cm2 at applied gate bias levels of about 1 V above threshold for an EOT of less than 1.4 nm and be detrimental to device performance and/or reliability.
One possible approach for decreasing EOT without increasing tunneling leakage current may involve substituting alternative oxides with dielectric constants (K) that could exceed that of SiO2. Silicon dioxide has a dielectric constant of approximately 3.9. For example, it may be desirable to obtain oxides with dielectric constants ranging from approximately 10 to more than 30. However, dielectric materials with higher vales of K generally tend to have relatively small band gaps of about 5 to 6 eV, as compared to about 9 eV for SiO2, which can also contribute to undesirable high tunneling leakage current in semiconductor devices despite a relatively high dielectric constant.
Silicon nitride and silicon oxynitride alloys have been proposed as the first generation of alternative gate dielectric materials. Silicon nitride and silicon oxynitride alloys have dielectric constants of approximately 7.6 and 5.5 to 6.0 respectively. For example, C. J. Parker, G. Lucovsky and J. R. Hauser, IEEE Electron. Device Lett. (1998); Y. Wu and G. Lucovsky, IEEE Electron. Device Lett. (1998); and H. Yang and G. Lucovsky, IEDM Digest, (1999) propose oxide-nitride and oxide-oxynitride alloy stacked dielectrics with EOT projected to be greater than about 1.1 to 1.2 nm before tunneling leakage at approximately 1 V is increased above 1-5 A/cm2. The preparation of these stacked dielectrics proposes two 300° C. remote plasma process steps: i) plasma-assisted oxidation to form Si—SiO2 interface layers ranging in thickness from about 0.5 to 0.6 nm, and ii) remote plasma-enhanced chemical vapor deposition (RPECVD) to deposit either a nitride or an oxynitride (e.g., (SiO2)x(Si3N4)1−x with x˜0.5) dielectric film in the dielectric stack. After deposition, a low thermal budget, e.g., 30 second, 900° C., rapid thermal anneal (RTA) has been proposed in an attempt to achieve chemical and structural relaxation. This RTA may promote optimized performance in IGFET devices [G. Lucovsky, A. Banerjee, B. Hinds, G. Claflin, K. Koh and H. Yang, J. Vac. Sci. Technol. B15, 1074 (1997)]. Stacked nitride and oxynitride gate dielectrics may display improved performance and reliability with respect to thermally-grown oxides of the same EOT. Nonetheless, these gate dielectrics typically have EOT of greater than 1.1 to 1.2 nm in order to attempt to maintain direct tunneling leakage below 1 A/cm2. The nitride and oxynitride layers of these devices may be sufficiently thick to minimize or stop boron out-diffusion out of p+ polycrystalline Si gate electrodes in the p-channel IGFETs [Y. Wu, et al., Vac. Sci. Technol. B17 1813 (1999)].
Other high-K dielectrics have been proposed (e.g., a K greater than 8) including TiO2 [J. Yan, D. C. Gilmer, S. A. Campbell, W. L. Gladfelter and P. G. Schmid, J. Vac. Sci. Technol. B 14, 1706 (1996).], Ta2O5 [H. Shinrike and M. Nakata, IEEE Trans. on Elec. Devices 38, 544 (1991)], Al2O3 [L. Manchanda, W. H. Lee, J. E. Bower, F. H. Baumann, W. L. Brown, et al., IEDM Tech. Dig., p. 605 (1998)], ZrO2, [R. B. van Dover, et al., IEEE Electron Device Lett., 19, 329, (1998)] and Zr(Hf)O2—SiO2 (also designated as Zr(Hf)-silicates; see van Dover et al.). These materials may not demonstrate the targeted goals of capacitance with decreased tunneling or leakage currents that may be desirable for silicon CMOS devices. For example, some of these materials, e.g., TiO2 and Ta2O5 may exhibit tunneling or leakage currents in CMOS devices with EOT less than 1 nm that are greater than 1-5 A/cm2. Using these and other dielectrics, the ultimate performance of the materials with EOTs extending to about 0.5 nm may be limited due to the oxidation of the silicon substrate that can occur during thermal chemical vapor deposition (CVD) or during post-deposition processing, such as, for example, thermal anneals, to fully oxidize the deposited thin films. This oxidation contributes to EOT, and in combination with the contribution of EOT of the high-k material makes it difficult to reduce the composite value of EOT to ˜0.5 nm.
Another high-K dielectric is non-crystalline Al2O3. The dielectric constant of Al2O3 is generally about nine or less, but Al2O3 has a band gap of more than 7 eV and conduction and valence band offset energies greater than 2 eV. However, because of its increased bond-ionicity with respect to SiO2 non-crystalline Al2O3 dielectric films may display a high value of interfacial fixed negative charge, e.g., greater than 1012 cm−2, as compared to less than 1011 cm−2 for SiO2 dielectrics, at interfaces with Si, or at interfaces with superficially thin (<0.5-1.0 nm) non-crystalline SiO2 in contact with Si (R. S. Johnson, et al, J. Vac. Sci. Technol. A 19, 1353 (12001)). This high value of fixed charge has been correlated with electron and hole mobility degradation in the channel of IGFET devices and can potentially contribute to a reduction in the dimensionally-scaled drive current by factors of two or more. Accordingly, the gains in device capacitance derived from the increased value of K may be diminished.
There may be other problems in the application of dielectric materials into aggressively scaled MOSFET devices. The various problems that can be experienced include i) high values of interfacial fixed charge that are generally positive ii) ion and atom transport, iii) high reactivity with ambient gases, giving rise to incorporation or water or hydroxyl groups, and iv) lower than anticipated tunneling currents due to reduced electron masses associated with the electronic structure, e.g., because the lowest conduction band has d-state properties. This last effect may be more apparent in transition metal oxides than in rare earth oxides. Other process integration issues may relate to the combined effects of their hydrophyllic nature and oxygen ion transport that can promote changes in interface bonding during post-deposition thermal process steps, including dopant activation of atoms in source and drain contacts to the channel in a MOSFET device.
Other high-K dielectric materials include non-crystalline silicate and aluminate alloys, which are generally non-stoichiometric and may not correspond to the composition of a particular crystalline phase. For example, hafnium silicate and aluminate alloys in the alloy composition range from ˜25% to at most 50% HfO2 have been proposed, as well as Zr silicate and aluminate alloys. Hafnium silicates may have reduced reactivity with Si substrates and the like. However, one drawback for both group IVB silicates may be their thermal stability against chemical phase separation into ZrO2 or HfO2, and a relatively low content silicate alloy (less than 10% ZrO2 or HfO2 as determined by the concentration of the eutectic in the equilibrium phase diagram), and crystallization of the ZrO2 or HfO2 phase. Thermal instability generally occurs at temperatures of ˜900° C. for low ZrO2 content Zr silicate alloys, and at temperature ˜1000° C. for low HfO2 content Hf silicates. Less is understood about chemical phase separation in aluminate alloys; however, there is some evidence for crystallization in Hf aluminate alloys. Decreases in K upon alloying with either SiO2 or Al2O3 may be significant. For example, the Zr and Hf silicate alloys that display the greatest amount of thermal stability against crystallization have dielectric constants less than 15 Nonetheless, they display reduced direct tunneling with respect to their respective end-member elemental oxides because of mitigating factors, such as the tunneling effective mass, that decreases as the transition metal oxide fraction increases. The precursor bonding states that drive the chemical phase separation can be a function of the degree of rigidity or over-constrained bonding in the non-crystalline alloy, particularly in the composition range of about 25 to 50% ZrO2 or HfO2. The increased rigidity of these alloys relative to non-crystalline SiO2, and nano- or micro-crystalline ZrO2 or HfO2, is the driving force for the chemical separation. The separated state is lower in energy, but also has a significantly reduced dielectric constant that renders phase separated dielectrics not useful for certain applications. In addition, the rigidity of these low ZrO2/HfO2 content silicate films may result in i) defects in the bulk of the film that cannot be compensated by hydrogen or deuterium, and leads to electron injection and trapping under biased conditions, and also ii) defect formation at the semiconductor dielectric interfaces, e.g., silicon atom dangling bonds in the strained silicon in contact with the dielectric film, and/or a superficially thin region with predominantly Si suboxide or Si—O bonding.
Other potential problems encountered with various high-K dielectrics may relate to: (1) the crystallization of the deposited films during either deposition or post-deposition processing, (2) the low dielectric constants of the bulk films that may be insufficient to meet the targeted goals, and (3) the formation of interfacial silicon oxides, or low content silicon oxide alloys (e.g., silicates) that may limit the attainable effective values of the K for the resulting stacked dielectric structure. For example, it is believed that oxidation of the silicon substrate during deposition or post-deposition processing may mitigate many of the gains of high-K layers with respect to achievable capacitance, whereas crystallization has the potential to open up alternative conduction pathways, the possibility of anisotropic dielectric constant behavior, and the potential to produce surface roughening.
The formation of interfacial silicide bonds may result in undesirable interfacial defects. Such defects may occur in the form of fixed positive charge or interface traps. Thus, it may be desirable to employ a thin dielectric interface layer of SiO2 between the dielectric layer and the silicon substrate. Utilizing such interfacial layers with known insulating film dielectrics, however, may be disadvantageous in that they may limit the dielectric stacks from having sufficient capacitance to meet the ever-increasing scaling demands of CMOS devices. Additionally, this use of interfacial layers may also limit the incorporation of high-K oxides into devices that employ semiconductor substrates other than silicon such as, for example, silicon carbide, gallium nitride (SiC and GaN, respectively) and compound semiconductors such as, (Al,Ga)N, GaAs, (Al,Ga)As, (In,Ga)As, GaSb, (Al,Ga)Sb, (In,Ga)Sb, as well as nitride, arsenide and antimonide quaternary III-V alloys.